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Large-Scale IC Design & Verification
Supporting SoC chip planning and verification, timing verification and standard cell library characterization and verification to predict and prevent design problems in advance, while enabling customers to efficiently create Standard Cell Library.
Circuit Simulation
Digital circuit simulation involves utilizing computer software to simulate the operation of digital circuits, validating their design correctness and performance. This process enables the examination of logic functionality, timing relationships, and digital electrical characteristics under various digital input conditions. Digital circuit simulation helps to identify and address design issues in advance, reducing the costs and time required for actual manufacturing and debugging. It has a direct and critical impact on the quality of chip design and products, as well as production efficiency.
Primarius VeriSim, an advanced digital simulator, features high-performance simulation engines and constraint solvers. By catering comprehensively to the needs of system-level, behavioral-level, RTL-level, and gate-level digital circuit simulation, VeriSim provides a comprehensive solution for digital design verification.
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Standard Cell
The Standard Cell Library is a standardized circuit cell library that plays a vital role in integrated circuit design. It encompasses a range of logic gate circuits that enable the implementation of complex digital circuit designs. It's usually provided by foundries for IC designers to optimize chip PPA.
Primarius Standard Cell Library solution employs advanced distributed parallel architecture technology and cutting-edge cell circuit analysis and extraction algorithms. Empowered with our high-precision SPICE simulator, it is represented by the fast and high-precision standard cell library characterization platform NanoCell, providing a complete solution for automated design, library characterization, and verification of standard cell libraries.
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Library Characterization
NanoCell
Standard Cell Library Characterization Solution
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Library Validation
LibWiz
Standard Cell Library Validation Solution
Design & Verification
SoC design and verification refers to the comprehensive development process of System-on-Chip (SoC), including architecture design, IP selection, integration, functional verification, and performance validation. This process utilizes hardware description languages (such as Verilog or VHDL) and employs simulation and verification tools to ensure design correctness and performance. In IC manufacturing, SoC design and verification play a crucial role, facilitating the early detection and resolution of design issues, thus reducing the costs and time required for actual manufacturing and debugging.
Primarius provides a suite of SoC circuit design and verification solutions, represented by the gate-TR mixed-level timing analysis tool TRASTA, Adaptable to various design requirements, our solutions help to enhance chip design reliability, accelerate time to market, and reduce costs and risks, thereby assisting IC designers in efficiently achieving design goals.
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Timing Analysis
TRASTA
Gate-TR Mixed-Level Timing Analysis Solution
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Floor Planning
NavisPro
Hierarchical SoC Design Planning Solution
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Signal Integrity Analysis
NanoSpice SI
NanoSpice Signal Integrity Solution
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Power Design Analysis
PTM
Power Device Design Verification
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ESD Verification
ESDi
Chip-level HBM ESD Analysis Platform
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Chip-to-Package Connectivity Verification
PadInspector
Chip-to-Package Connectivity Verification Solution
